Physical Design / Implementation Manager---- ravikir@xilinx.com

This position will be critical to shaping the next generation of FPGA products from Xilinx, the leader in FPGAs. The successful candidate for this position will join a technology leader, a rapidly growing organization and be an integral member of a skilled and motivated team. The job will involve building the next generation devices for Xilinx using a leading edge SoC and FPGA implementation flow. The successful candidate will have physical implementation responsibility for these next generation FPGA devices.
Job Responsibilities

· Responsible for full chip physical implementation
· Build and manage a world-class physical implementation team
· Responsibilities include synthesis, place and route, design closure/signoff, DFT, DFM and integration into a custom fabric
· Responsible of physical implementation planning and delivery
· Interacting with physical design teams and digital design teams across multiple geographic locations
· Coach and resolve technical issues of team members


Job Requirements
· BTech/BE/BSEE with 12+ years of experience. MTech/ME/MSEE preferred.
· Strong success taping out multiple DSM SoC/ASIC chips at 65nm or below
· Proven experience with high-speed interface/DDR integration
· Deep understanding of all aspects of SoC/ASIC design and implementation, including package, test and foundry interfaces
· Hands-on experience with DSM SoC/ASIC methodologies including advanced DFM, DFT, OCV, signoff methodologies
· Strong experience using synthesis, place and route tools from Synopsys or Cadence
· Experience with post Silicon bring up and debug
· 4+ years of experience managing a physical design team
· Should be motivated, self-starter.
· Excellent communication skills


Please contact ravikir@xilinx.com